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IEEE Cluster 2013 Conference
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Monday, September 23 • 8:30am - 4:30pm
Full day Tutorial - Programming for the Intel Xeon Phi (MIC) LIMITED

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Limited Capacity seats available

Hands-on: Interactive session a full day tutorial on how to use the new Intel Xeon Phi Coprocessor, also known as a MIC in high performance computing environments. This will be a course for intermediate to advanced users, where the audience is expected to be familiar with C or Fortran, OpenMP, as well as MPI.

While the MIC is x86 based, and capable of running most user codes with little porting effort, the MIC architecture has significant features that are different from those of present x86 CPUs, and optimal performance requires an understanding of the possible execution models and details of the architecture. The tutorial will be divided in four sections: Introduction to the MIC Architecture; Native Execution and Optimization; Offload Execution; and Symmetric Execution. In each section the users will spend approximately half of their time experimenting with guided hands-on exercises, as shown in the draft agenda: Draft Agenda


Monday September 23, 2013 8:30am - 4:30pm
07th Floor - Circle City 07 (Hilton) 120 W. Market St, Indianapolis, IN

Attendees (1)